What Is The Minimum Number Of Clock Cycles Needed To Load A 16-bit Register?

Introduction

There are a big number of timing parameters in the DDR standard, simply when yous work with DDR4 SDRAM yous'll oft discover yourself revisiting or reading nigh a handful of timing parameters more oftentimes than others. So, in this commodity we'll examine simply these oft occurring timing parameters by looking at them in the context of a command.

These timing parameters are a hard thing to remember, they tend to sideslip out of your head. The accompanying commodity, Timing Parameter Cheat Sheet, can be used as a reference to recollect what a specific timing parameter means.

Notation: All pictures below were taken from the DDR4 JEDEC specification and a Micron retention part spec. Links to them tin can be found in the Reference section.

Actuate Timing

The ACTIVATE control is used to open up a row within a bank. In Understanding the Basics nosotros saw that every bank has a set of sense amps, then one row tin can remain agile per banking concern. With ACTIVATE in that location are 3 timing parameters we should know almost: tRRD_S, tRRD_L, tFAW

Parameter	Part
tRRD_S	When issuing consecutive ACTIVATE commands to banks of different bank groups, the Actuate commands have to be separated by tRRD_S (row-to-row delay--brusque)
tRRD_L	If the banks belong to the same bank group, their ACTIVATEs have to be separated past tRRD_L (row-to-row delay--long)
tFAW	Iv Activate Window or sometimes also called 5th Activate Window is a timing restriction. tFAW specifies a window within which simply four activate commands can be issued. So, you can consequence ACTIVATE commands back-to-dorsum with tRRD_S between them, only one time you lot have completed four activates you cannot issue another one until the tFAW window expires.

Table one: Actuate command timing parameters

Figure i: tRRD timing

Figure 2: tFAW timing

REFRESH Timing

In order to ensure data stored in the SDRAM is not lost, the memory controller has to issue a REFRESH command at an average interval of tREFI. Simply before a REFRESH can exist applied, all banks of the SDRAM have to be Precharged and idle for a minimum fourth dimension of tRP(min). In one case a REFRESH command is issued, there has to be a delay of tRFC(min) before the next valid command is issued (except DES control).

Observe how I mentioned that tREFI is the "boilerplate" interval between REFRESH commands. This is because you can push-out (or pull-in) a certain number of refresh commands and make upward for it later. This style was added to DDR4 to overcome the operation penalization due to refresh lockout at the higher densities. The number of refresh commands that tin exist postponed depends upon the Refresh Mode (1x, 2x or 4x) which can be set in the SDRAM's Fashion Register MR2.

Parameter	Part
tREFI	The device requires REFRESH commands at an average interval of tREFI
tRP	Precharge time. The banks accept to be precharged and idle for tRP before a REFRESH command tin be practical
tRFC	Filibuster betwixt the REFRESH command and the next valid control, except DES

Table two: Refresh command timing parameters

Effigy 3: REFRESH timing

Effigy iv: Postponing REFRESH command

READ Timing

The READ timing parameters can exist cleaved up into 3 categories - Overall read timing, Clock-to-Strobe relationship and Data Strobe-to-Data relationship. Refer to DRAM-read-functioning to empathise the basics.

Parameter	Role
Read Timing
CL (CAS Latency)	CAS is the Column-Address-Strobe, i.east., when the column address is presented on the lines. CL is the delay, in clock cycles, between the internal READ command and the availability of the beginning bit of output data. It is divers in the MR0 way annals. SDRAM data sheets typically specific what the CL needs to be gear up for a particular frequency of functioning. *Run across Fig vii*
AL (Additive Latency)	With AL, the device allows a READ control to be issued immediately after the Actuate command. The command is held for the time of AL earlier it is issued inside the device. This feature is supported to sustain college bandwidths/speeds in the device.
RL (Read Latency)	This is the overall read latency and is defined as RL = CL + AL
tCCD_S & tCCD_L	Bank accesses to unlike banks' groups require less time delay between accesses than depository financial institution accesses to within the same bank's group. Bank accesses to unlike banking concern groups require tCCD_S (or brusk) delay between commands while banking concern accesses within the aforementioned bank group require tCCD_L (or long) delay between commands.
Clock to Information Strobe relationship
tDQSCK (MIN/MAX)	describes the allowed range for a ascent information strobe edge relative to the clock CK_t, CK_c
tDQSCK	is the actual position of a rising strobe edge relative to CK_t, CK_c
tQSH	describes the information strobe high pulse width
tQSL	tQSL - describes the information strobe low pulse width.
Data Strobe to Information relationship
tDQSQ	This describes the latest valid transition of the associated DQ data pins. From the picture below you'll see that it is the fourth dimension between when DQS transitions to the left edge of the DQ data-eye
tQH	Is the earliest invalid transition of the associated DQ pins. From the picture below you'll run into that it is the time from when DQS goes loftier to the correct egdge of the DQ data-heart.

Tabular array 3: Read command timing parameters

Figure 5: Consecutive READs to different Bank Groups. In this figure AL=0, CL = 11, so RL = 11. Observe how the read data burst (DQ bus) from the 2d READ immediately follows the first without any gap. Also find tCCD_S between the 2 consecutive reads.

Figure six: Non-Sequent READs to different Banking concern Groups

Figure 7: Analogy of tCCD_S and tCCD_L

Figure 8: Illustrating CK-DQS and DQS-DQ relationships

WRITE Timing

Following similarly to the READ ...

Parameter	Function
Write timing
CWL (CAS Write Latency)	CWL is the delay, in clock cycles, between the internal WRITE command and the availability of the start bit of input information. It is divers in Mode Register MR2.
AL (Additive Latency)	With AL, the device allows a WRITE command to exist issued immediately after the Actuate command. The command is held for the time of AL before it is issued inside the device. This feature is supported to sustain higher bandwidths/speeds in the device.
WL (Write Latency)	This is the overall write latency and is defined as WL = CWL + AL
tCCD_S & tCCD_L	Banking company accesses to different banks' groups require less fourth dimension delay betwixt accesses than bank accesses to within the same bank'southward grouping. Bank accesses to unlike bank groups require tCCD_S (or brusque) delay between commands while depository financial institution accesses within the same depository financial institution group require tCCD_L (or long) delay between commands.
Clock to Data Strobe relationship
tDQSS (MIN/MAX)	describes the allowed range for a ascent information strobe edge relative to CK
tDQSS	is the actual position of a ascension strobe edge relative to CK
tDQSH	describes the data strobe high pulse width
tDQSL	describes the data strobe low pulse width
tWPST	This of this equally "postal service-write". It is the time from when the final valid information strobe to when the strobe goes to HIGH, not-drive level.
tWPRE	This of this every bit "pre-write". It is the time betwixt when the data strobe goes from non-valid (Loftier) to valid (LOW, initial drive level).

Table iv: Write command timing parameters

Effigy ix: WRITE timing parameters

Fashion Register Timing

SDRAMs provide a number of features, functions and settings which can exist programmed using the 7 Mode Registers. These registers tin be programmed using the MRS (Mode Register Set) control. The Way Registers are prepare during initialization and thereafter they can exist changed at whatsoever fourth dimension during normal functioning. Fashion Annals setting is governed by 2 timing parameters.

Parameter	Function
tMRD	MRS command cycle time. Information technology is the time required to complete the WRITE performance to the mode annals and is the minimum time required between the two MRS commands shown in the tMRD Timing figure.
tMOD	is the minimum time required from an MRS control to a non MRS command, excluding DES.

Table v: Mode register command timing parameters

Figure 10: tMRD timing

Figure 11: tMOD timing

References

• JESD79-49B specification
• Micron Specification

Source: https://www.systemverilog.io/understanding-ddr4-timing-parameters

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